Digi Times

Accurate Analysis of Multi-Gigabit Systems Using HSPICE

Connecting an application processor to a DRAM chip through a 3200 Mbps LPDDR4 interface is not any easier than routing a 2600 MHz 4G LTE antenna. While RF front ends enjoy ceramic packages and careful ...
Nature

Signal Integrity and Eye Diagram Analysis in High-Speed Interconnects

Signal integrity is a critical design consideration in modern electronic systems, particularly those that depend on high-speed interconnects. As data rates climb and interconnect geometries become ...
EDN

Product how-to: HSPICE accurately analyzes gigabit circuits like DDR4 & USB3

Connecting an application processor to a DRAM chip through a 3200 Mbps LPDDR4 interface is not any easier than routing a 2600 MHz 4G LTE antenna. While RF front ends may enjoy ceramic packages and ...
Electronic Design

Eye-Diagram Analysis Speeds DDR SDRAM Validation

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...